Your mission
The role is part of the circuit design team at EXTOLL. The team is tasked with delivering high quality and best performing solutions for high-speed data interfaces. A commitment to on-time delivery and strong focus on design quality and customer orientation is the foundation of all we do:
- Develop and maintain SystemVerilog real number behavioral models of analog/full-custom circuits.
- Work with system architects and HDL designers to build up a SystemVerilog based model of a complete complex mixed signal IP.
- Closely work with the Functional Verification team to resolve issues and improve verification and model quality.
- Develop and refine directed test cases to enable test and debugging of model and IP.
- Contribute to the design and implementation of the mixed signal verification methodology and model validation setup to continuously improve quality.
- Work closely and cross-functional across different groups to support a successful and on-time product release.